The present invention relates to a semiconductor component, in particular to a semiconductor with an improved interlayer interconnect scheme.
The semiconductor is of the type in which:
(a) A semiconductor substrate contains a first layer of a first conduction material;
(b) above the first layer is a second layer of a second conduction material;
(c) the second layer is provided with an opening;
(d) the first layer has a depression under the opening;
(e) the first and second layers are interconnected electrically by a conducting layer; and
(f) the conducting layer contacts the first layer in the depression and the second layer at the wall of the opening.
Such a semiconductor component is described U.S. Pat. No. 4,408,384 issued on Oct. 11, 1983 to Lewis et al. which is hereby incorporated by reference especially with reference to FIG. 9. This semiconductor component has a source contact which contacts the source zone, located on the substrate surface, at an opening, and also an epitaxial layer, located under this source zone, in a depression. The source zone opening and the depression in the epitaxial layer under it are produced jointly by anisotropic etching, through which a V-shaped groove is formed. The edges of the groove are aligned alongside the surfaces of the epitaxial layer. In order to establish good cotact between the relatively weakly doped epitaxial layer and the source zone, the epitaxial layer must be contacted over a relatively large area, i.e. to a great depth. Due to the physical characteristics of anisotropic etching, the process is associated with a relatively great loss of area on the surface of the semiconductor component.